<div>About Corinex: At Corinex, we are driving the future of energy with cutting-edge Broadband over Power Line (BPL) technology. As a global leader in smart grid solutions, we enable utilities to enhance grid visibility, flexibility, and decarbonization- supporting the seamless integration of renewable energy, electric vehicles, and heat pumps into the power grid. Headquartered in Vancouver, Canada, Corinex is the market leader in Europe, particularly in Spain, where our BPL solutions are deployed by major DSOs (Distribution System Operators) to improve grid operations. With successful implementations across global markets, our technologies accelerate the transition to a more sustainable, decentralized, and efficient energy infrastructure. Recognized as a key contributor to industry standards and a 2024 Deloitte Technology Fast 50 winner, Corinex is shaping the future of smart energy. To strengthen our team in Spain, we are seeking an experienced and motivated Engineer, Design Verification.  About the role: We are looking for an Engineer, Digital Developer to join our Valencia R&amp;D team. For this role, we are open to new grads or candidates with experience. The candidate will be integrated into a dynamic, cross-functional, experienced team to develop block and chip-level design and functional verification tests in Verilog and C, for million-plus gate ASICs targeted for BPL networking applications. The job will involve understanding DSP and networking algorithms, efficiently translating those into structured RTL, designing and implementing test benches, verifying blocks, supporting integration and emulation into prototypes. This full-time, remote position requires a strong foundation in semiconductor design methodologies, CAD tools, and scripting to apply their expertise in a dynamic and innovative environment.  Responsibilities:<ul><li>Participate in all project stages: design, implementation, hardware/system bring-up and system/product delivery of our BPL communications system.</li><li>Design / Modelling in SystemC or equivalent. Code RTL hardware and directed and random test-case development. The usage of coverage tools is expected. </li><li>RTL verification or gate level (VHDL, C, System Verilog / UVM, formal proof…)</li><li>Top-level integration</li><li>Work with third-party vendors to define customization requirements of third-party IPs.</li><li>Work with the physical design teams, reviewing and providing guidance in floor planning, power analysis, synthesis and timing analysis.</li><li>Collaborate with hardware and software teams to integrate microelectronic solutions.</li><li>Work with the verification team on pre-silicon verification tasks such as reviewing the test plans, coverage analysis, full-chip simulation and emulation, performance and power analysis and debug.</li><li>Stay updated with the latest advancements in microelectronics and apply them to projects.</li></ul> Qualifications: <ul><li>Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or a related field.</li><li>Strong knowledge of semiconductor ASIC design methodologies and flows.</li><li>Extensive experience with RTL modelling (VHDL or Verilog), simulation, logic synthesis, and static timing analysis.</li><li>Proficiency in CAD tools and simulation software (e.g., Cadence, SPICE) with hands-on experience conducting simulations and testing to meet design specifications.</li><li>Familiarity with front-end and back-end design flows, including synthesis, static timing analysis, floor planning, and timing closure.</li><li>Solid understanding of semiconductor devices and fabrication processes.</li><li>Proficiency in scripting languages such as Perl, Python, and Shell.</li><li>Strong grasp of Design-for-Test (DFT) methodologies, including Scan and Built-In Self-Test (BIST).</li><li>Experience in full-chip integration of complex SoC designs.</li><li>Expertise in high-speed protocols, particularly Ethernet.</li><li>Experience in architectural, micro-architectural, and register-level specifications.</li><li>Background in one or more domains: networking, embedded systems architecture, computer architecture, and machine learning accelerators.</li><li>Ability to work effectively in a collaborative team environment.</li><li>Strong communication skills in English.</li></ul></div>

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<div id="ember56" class="ember-view organization-about-module__content-consistant-cards-description">Corinex is a leading provider of BPL-based grid flexibility solutions, enabling the digitalization of the distribution system where energy consumers connect. Our solutions maintain network capacities and steer low-carbon technologies (LCTs) to consume local generation. Our grid asset management solution utilizes existing grid infrastructure and enables edge computing, high-speed transmission, real-time grid performance data, device management, and security at the edge of the grid. Our broadband end-to-end solution, integrates distributed energy devices and enables real-time energy data, analytics and predictive models, with the highest level of security. </div>
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Engineer, Digital Developer

<div>About Corinex: At Corinex, we are driving the future of energy with cutting-edge Broadband over Power Line (BPL) technology. As a global leader in smart grid solutions, we enable utilities to enhance grid visibility, flexibility, and decarbonization- supporting the seamless integration of renewable energy, electric vehicles, and heat pumps into the power grid. Headquartered in Vancouver, Canada, Corinex is the market leader in Europe, particularly in Spain, where our BPL solutions are deployed by major DSOs (Distribution System Operators) to improve grid operations. With successful implementations across global markets, our technologies accelerate the transition to a more sustainable, decentralized, and efficient energy infrastructure. Recognized as a key contributor to industry standards and a 2024 Deloitte Technology Fast 50 winner, Corinex is shaping the future of smart energy. To strengthen our team in Spain, we are seeking an experienced and motivated Engineer, Design Verification.&nbsp; About the role: We are looking for an&nbsp;Engineer, Digital Developer&nbsp;to join our Valencia R&amp;D team. For this role, we are open to new grads or candidates with experience. The candidate will be integrated into a dynamic, cross-functional,&nbsp;experienced team to develop block and chip-level design and functional verification tests in Verilog and C, for million-plus gate ASICs targeted for BPL networking applications. The job will involve understanding DSP and networking algorithms, efficiently translating those into structured RTL, designing and implementing test benches, verifying blocks, supporting integration and emulation into prototypes. This&nbsp;full-time, remote&nbsp;position&nbsp;requires&nbsp;a strong foundation in semiconductor design methodologies, CAD tools, and scripting to apply their expertise in a dynamic and innovative environment.&nbsp; Responsibilities:<ul><li>Participate in all project stages: design, implementation, hardware/system bring-up and system/product delivery of our BPL communications system.</li><li>Design / Modelling in SystemC or equivalent. Code RTL hardware and directed and random test-case development. The usage of coverage tools is expected.&nbsp;</li><li>RTL verification or gate level (VHDL, C, System Verilog / UVM, formal proof…)</li><li>Top-level integration</li><li>Work with third-party vendors to define customization requirements of third-party IPs.</li><li>Work with the physical design teams, reviewing and providing guidance in floor planning, power analysis, synthesis and timing analysis.</li><li>Collaborate with hardware and software teams to integrate microelectronic solutions.</li><li>Work with the verification team on pre-silicon verification tasks such as reviewing the test plans, coverage analysis, full-chip simulation and emulation, performance and power analysis and debug.</li><li>Stay updated with the latest advancements in microelectronics and apply them to projects.</li></ul> Qualifications: <ul><li>Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or a related field.</li><li>Strong knowledge of semiconductor ASIC design methodologies and flows.</li><li>Extensive experience with RTL modelling (VHDL or Verilog), simulation, logic synthesis, and static timing analysis.</li><li>Proficiency in CAD tools and simulation software (e.g., Cadence, SPICE) with hands-on experience conducting simulations and testing to meet design specifications.</li><li>Familiarity with front-end and back-end design flows, including synthesis, static timing analysis, floor planning, and timing closure.</li><li>Solid understanding of semiconductor devices and fabrication processes.</li><li>Proficiency in scripting languages such as Perl, Python, and Shell.</li><li>Strong grasp of Design-for-Test (DFT) methodologies, including Scan and Built-In Self-Test (BIST).</li><li>Experience in full-chip integration of complex SoC designs.</li><li>Expertise in high-speed protocols, particularly Ethernet.</li><li>Experience in architectural, micro-architectural, and register-level specifications.</li><li>Background in one or more domains: networking, embedded systems architecture, computer architecture, and machine learning accelerators.</li><li>Ability to work effectively in a collaborative team environment.</li><li>Strong communication skills in English.</li></ul></div>

Engineer, Digital Developer

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Corinex

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